1. Field of the Invention
The present invention relates to a semiconductor device and a semiconductor module, and relates in particular to a semiconductor device and module constituting a circuit or a system by a semiconductor chip incorporated therein and a wiring line, etc.
2. Description of the Related Art
To produce a hybrid integrated circuit for installation in an electronic apparatus, a conductive pattern is formed on a printed circuit board, a ceramic substrate or a metal substrate, and an active element, such as an LSI or a discrete TR, and a passive element, such as a chip capacitor, a chip resistor or a coil, are mounted thereon. The conductive pattern and these elements are electrically connected to provide a circuit capable of performing a predetermined function.
FIG. 24 is a diagram of such a circuit, an audio circuit, the elements of which are mounted as shown in FIG. 25.
In FIG. 25, straight, peripheral lines describe a rectangular substrate 1 having a surface that is, at the least, insulated. Adhered thereto is a conductive pattern 2, composed of Cu. The conductive pattern 2 is composed of an external connecting electrode 2A, a wire line 2B, a die pad 2C, a bonding pad 2D, and an electrode 4, fixed to the passive element 3.
A bare chip, consisting of a TR, a diode, a composite element or an LSI, is soldered to the die pad 2C, and the electrode on the chip and the bonding pad 2D are electrically connected by fine metal lines 5A, 5B and 5C, each of which is generally divided into a low signal portion and a high signal portion. An Au or Al line 5A of about 40 μm φ is employed for the low signal portion, and an Au or Al line of about 100 to 300 μm φ is employed for the high signal portion. Especially, since the high signal portion has a large diameter, while taking manufacturing costs into account, an Al line 5B of 150 μm φ and an Al line 5C of 300 μm φ are employed.
A power TR 6 though which a large current flows is securely fixed to a heat sink 7 on a die pad 2C in order to prevent a rise in the temperature of the chip.
The line 2B is extended to various locations in order to form the circuit for the external drawing electrode 2A, the die pad 2C, the bonding pad 2D and the electrode 4. Further, when lines intersect each other because of their disposition on the chip and when they must be extended, jumper lines 8A and 8B are employed.
An example semiconductor device to be mounted in the substrate 1 is a semiconductor device packaged using an insulating resin. As such a packaged semiconductor device there is a lead frame type semiconductor device, wherein a semiconductor chip is mounted in a lead frame and the resultant structure is packaged using an insulating resin; a support substrate type semiconductor device, wherein a semiconductor chip is mounted on a ceramic support substrate, a printed circuit board or a flexible sheet, and the resultant structure is packaged using an insulating resin; or a plated type semiconductor device, wherein a semiconductor chip is mounted on a plated electrode and the resultant structure is packaged. It should be noted that the plated type semiconductor device is described in detail in JP-A-3-94431.
FIG. 26A is a schematic diagram showing the plated type semiconductor device. Conductive paths 10A to 10D are formed of a plated film, a semiconductor chip 11 is securely bonded to the die pad 10A, and the bonding pad on the semiconductor chip 11 and the plated bonding pad 10B are electrically connected by a fine metal line 12. A passive element 13 is bonded between the electrodes 10C and 10D via a brazing material. And since the plated film is embedded in the insulating resin without using a support substrate, a thin semiconductor device can be provided.
As is described above, a semiconductor device packaged using various methods is mounted on the substrate 1. However, when a lead frame type semiconductor device is packaged, since lead projects outward from the package, the area of the substrate occupied by the device is expanded, and the size of the substrate must accordingly be increased. In addition, the lead frame could be cut or a burr could be left on the lead. Furthermore, for the support substrate type semiconductor device, since a support substrate is employed, the semiconductor device will be thicker, and accordingly, the weight of the device will be increased. Further, although a thin and compact plated type semiconductor device can be made because no support substrate is employed and because no lead projects outward from the package, the following problem has arisen.
For the explanation of the problem in FIG. 26B an enlarged diagram is shown of a portion enclosed by a broken-line circle in FIG. 26A. Included in this portion is a conductive path 10B, which is formed by plating and is represented as a set of trigonal pyramids; solder 17; a substrate 15; and a conductive pattern 16 adhered to the substrate 15.
The plated film is generally deposited by electrolytic plating, and has a crystal structure that assumes a tapered pillar shape. This structure is represented by using the trigonal pyramids. Since when formed the plated film is thin and has a polycrystalline structure, it is mechanically weak, and cracks tend to occur due to differences in the thermal expansion coefficient of the insulating resin. In addition, the grain boundary easily diffuses an externally supplied material. Thus as one problem, the flux used for soldering or an external ambient gas, such as moisture, may enter via the connection for the fine metal line 12, and at the grain boundary, cause deterioration of the connection strength. Further, as another problem, when an electrode 10B is formed using Cu plating, the solder layer underneath is diffused and eats into the plated film, thereby deteriorating the strength of the connection with the fine metal line.
In addition, when an elongated plated film is formed as a wire line, line disconnection may occur due to mismatching with the thermal expansion coefficient of the insulating resin. Similarly, when the plating type semiconductor device is mounted in the substrate, cracks also occur in wire lines due to mismatching with the thermal expansion coefficient of the substrate, and causes line disconnections or increases in line resistance. Especially when a long wire line is formed using the plated electrode 10B, stress is generated in proportion to the length. Therefore, differences in the thermal expansion coefficient of the insulating resin 14 or the substrate 15 aggravates defects in the plated film and degrades reliability even more.